Re-configurable mixed-mode integrated circuit architecture

ABSTRACT

An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

FIELD OF THE INVENTION

This invention relates generally to integrated circuit architecture, andmore particularly to a re-configurable integrated circuit architecturethat uses analog and digital building blocks to build a mixed-modeintegrated system.

BACKGROUND

Mixed mode electronic systems that use analog and digital buildingblocks in the industry may use programmable logic devices (PLD), complexprogrammable logic devices (CPLD), and/or field programmable gate arrays(FPGA) to implement the digital functional portion of the mixed modeelectronic system by programming the configuration switches in theprogrammable devices. However, the analog functions of the mixed modeelectronic system, which are interfacing, controlling or beingcontrolled by the digital functions, usually are specific and are notre-configurable. Moreover, these analog functions are not suitable to beintegrated on the same silicon with digital programmable devices becauseof the noise that the digital portion will inject into the commonsubstrate. Thus, currently-existing programmable analog functions areexpensive, specific to limited applications, and are mostly used forprototyping applications. Presently, existing programmable mixed modeintegrated devices use pre-defined or pre-configured analog functionscombined with a routing matrix that is suitable for digital signals toroute the analog signals, and a digital programmable array similar to aPLD, FPGA, DSP, or Micro Controller function. The routing matrix usesCMOS pass gates to route and connect the analog signals between theanalog functions. These metal oxide semiconductor (CMOS) pass gates,which are not suitable for passing analog signals with differentfrequencies and amplitudes limit the operating range of the analogfunctions and will also make it more prone to noise.

Therefore, there is a need in the art for a programmable mixed modearchitecture that integrates analog and digital functions and resolvesthe noise issue injected by the digital portion.

SUMMARY

The present invention provides a new way of routing, mixing, orconnecting the analog signal without limiting their performance. It alsomakes the analog functions programmable and re-configurable to variousanalog functions.

In one aspect of the invention, a mixed-mode integrated circuit systemincludes a plurality of analog input cells, a plurality of analog outputcells, an analog interconnect array, and a programmable digital portion.The input cells are configured to program various analog functions. Theoutput cells are configured to provide digital and/or analog outputscorresponding to the programmed analog functions. The interconnect arraymixes and directs the programmed analog functions into signalsindicative of the analog functions. The array selectively provides thesignals to the plurality of analog output cells. In one embodiment, theprogrammable digital portion includes a programmable logic device, Fieldprogrammable Gate array, macrocells, and a Phase Lock Loop (PLL).

In another aspect of the invention, the analog portion includes aplurality of analog input cells, a plurality of analog output cells, anda current sensing array. The analog input cells provide a plurality ofpredefined analog functions. The analog output cells generate digitaland/or analog signals corresponding to the predefined analog functions.The current sensing array converts predefined analog functions from theplurality of analog input cells into current signal, mixes and directsthe current signal, converts the current signal into voltage signal, andselectively provides the voltage signal to the plurality of analogoutput cells.

Other features and advantages of the present invention should beapparent from the following description, which illustrates, by way ofexample, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a mixed-mode integrated circuit architecture inaccordance with an exemplary embodiment of the present invention.

FIG. 2 illustrates a programmable analog current sensing interconnectarray according to an exemplary embodiment of the present invention.

FIG. 3 is a schematic diagram of a re-configurable analog input cellaccording to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a programmable analog output cellaccording to an embodiment of the invention.

DETAILED DESCRIPTION

In recognition of the above-stated problems associated with existingmixed-mode integrated circuit architectures, embodiments forre-configurable analog devices and functions are described. Inparticular, following exemplary embodiments integrate digital and analogfunctions with re-configurable digital and analog arrays into amixed-mode integrated circuit architecture. The analog functions includeanalog input cells, analog output cells, and an analog interconnectcurrent sensing matrix. Furthermore, the mixed mode architecture enablesintegration of various mixed-mode systems without separating analogcircuits/functions from digital functions. Consequently, for purposes ofillustration and not for purposes of limitation, the exemplaryembodiments of the invention are described in a manner consistent withsuch use, though clearly the invention is not so limited.

A mixed-mode integrated circuit architecture 100 in accordance with anexemplary embodiment of the present invention is illustrated in FIG. 1.In the exemplary embodiment, the mixed-mode architecture 100 includes ananalog portion 110 and a digital portion 160. The analog portion 110includes four re-configurable analog input cells 112-118, fourprogrammable analog output cells 120-126, and a programmable analoginterconnect current sensing array 150. However, the analog portion 110may be configured with any appropriate number of cells and/or currentsensing arrays to implement the mixed-mode circuit in a similar design.The re-configurable analog input cell 112-118 enables programming ofseveral analog functions using switches. The programmable analog outputcell 120-126 processes the current output signal of the interconnectcurrent sensing array 150 to a digital signal appropriate forinterfacing with the digital array 162.

The analog portion 110 further includes programmable voltage referencegenerator 102 that generates voltage references, which are accessible tothe re-configurable input/output cells 112-126 and direct analog inputports 148 coupled to the analog interconnect current sensing array 150.The direct analog input ports 148 are used to input analog signals thatdo not require processing by the analog input cells 112-118.

The digital portion 160 may include a programmable logic array 162, aphase lock loop (PLL) 166, a clock generator 168, and macro-cells 164with digital inputs/outputs that meet various interfacing standards. Inthe exemplary embodiment, the programmable logic array 162 includes 44input elements (22 non-inverted and 22 inverted input signals). Eight ofthe input elements are coupled to the analog output cells 120-126, andthe other 36 input elements are coupled to 18 external digital inputpins. However, the programmable logic array 162 may be implemented usingthe architecture similar to the conventional architecture ofprogrammable logic devices (PLD), field programmable gate arrays (FPGA),and/or other similar architectures. PLL 166 receives a referencefrequency from an oscillator that is multiplied and phase-lock looped bythe PLL block to provide high clock frequency and synchronization of thesignals in the macro-cells 164. In some embodiments, the PLL 166 may bemultiplexed with an external clock in the clock generator 168 to enableoperation of each output macro-cell 164 from a different clock source ifdesired. The clock generator 168 includes clock drivers and amultiplexer. The drivers receive the PLL output and drive the macrocells164 of the programmable logic array 162. The multiplexer enables receiptof the clock signal from an external source by bypassing the PLL 166.

In an alternative embodiment, the programmable analog interconnectcurrent sensing array 150 of the analog portion 110 is configured tooperate with conventional pre-defined input and output cells. However,unlike the conventional design of the array, the interconnect array 150of the alternative embodiment converts the output of the input cell fromvoltage to current so that crosstalk and noise coupling betweendifferent analog signals from different input cells are substantiallyreduced.

In a further embodiment, the analog input cells 112-118 and the analogoutput cells 120-126 of the analog portion operate in conjunction with aconventional design of the interconnect array. Hence, the output signalfrom the input cell is not converted from voltage to current, and theinput signal to the output cell need not be converted to voltage.Although this configuration may introduce some crosstalk and noisecoupling, the advantages of the programmability of the input and outputcells can be realized.

A programmable analog current sensing interconnect array 150 accordingto an exemplary embodiment of the present invention is shown in FIG. 2.The interconnect array 150 enables connection of the analog input cells112-118 to the analog output cells 120-126. Signals from the analoginput cells 112-118 representing the programmed analog functions areconverted to current and directed to the desired output cells byprogramming the volatile/non-volatile configuration switches of theinterconnect array 150. The processed signals are then transmitted tothe analog output cell(s) 120-126 through an operational amplifier 210,212, or 214 that acts as a current-to-voltage converter.

In the exemplary embodiment, a voltage-to-current converter circuit 202in the interconnect array 150 converts the output signal from input cellA into current. This voltage-to-current converter circuit 202 includesoperational amplifiers and transistor switches. Voltage-to-currentconverter 204 operates in similar manner with input cell B. Thus, byconverting the analog signals from voltage into current, the analoginterconnect array 150 substantially reduces crosstalk and noisecoupling between different analog signals from different analog inputcells.

The array 150 may also be used as a mixer for the different analogcircuits/signals generated from two or more re-configurable analog inputcells by operating the analog interconnect array 150 in a current mode.For example, by turning on both switches SW1 and SW2 in the same columnas output cell A, the analog signals generated from the twore-configurable input cells (i.e., input cell A and input cell B) aremixed in current before being passed to the selected analog output cell(i.e., output cell A). The array may further be used as a splitter bydirecting a current signal into more than one output cell. For example,by turning on both switches SW1 and SW3, the analog signal generatedfrom input cell A is directed into both output cell A and output cell B.

The analog interconnect array 150 also allows analog inputs that requireno processing by the input cell to enter the analog array 150 through avoltage-to-current converter circuit. The converted analog inputs maythen be mixed with other analog signals and directed to one or moreanalog output cells.

FIG. 3 is a schematic diagram of a re-configurable analog input cell 300according to an embodiment of the present invention. In the illustratedembodiment, the input cell 300 includes transistors SW14, SW15,capacitors C1, C2, adjustable resistors AR1-AR4, configuration switchesSW1-SW17, and an operational amplifier 304. The configuration switchesSW1-SW17 are controlled by volatile/non-volatile memory cells. Theconfiguration switches may be selected or deselected to configure theinput cell into desired analog functions.

Table 1 shows the configuration switches SW1-SW17 that may be turned onto generate the listed analog functions in accordance with an exemplaryembodiment. For example, a unity gain non-inverting amplifier may beconfigured by turning on switches SW2 an SW14. Other analogcircuits/functions, such as an integrator, a difference amplifier, adifferentiator, a comparator, a reference voltage generator,configurable/adjustable gain amplifier, and a current-to-voltageamplifier, may also be configured by turning on an appropriatecombination of switches as listed in Table 1. The list, however, isprovided for illustrative purposes only. Other circuits/functions can begenerated using different combinations of configuration switches. Forexample, switches SW14 and SW15 may also be used to generate asample-and-hold circuit.

TABLE 1 Re-configurable Analog Functions Functions ConfigurationSwitches Unity Gain Amplifier SW2, SW15 Integrator SW3, SW4, SW6, SW8,SW10 Difference SW4, SW6, SW9, SW10, SW11, SW7 Differentiator SW4, SW5,SW8, SW10 Comparator SW14, SW15 Voltage Reference SW2, SW13 GainAmplifier SW4, SW15, SW16 Current-to-Voltage Converter SW4, SW14, SW17

In the illustrated embodiment of FIG. 3, the output 310 of an analoginput cell 300 is coupled to the interconnect array 150 through avoltage-to-current converter 312. However, the output 310 of the analoginput cell 300 may also be coupled directly to the interconnectionmatrix 404 of the adjacent analog output cell 400 (i.e., bypass path tothe output cell) and/or to the input multiplexer 302 of another analoginput cell (i.e., bypass path to another input cell). Hence, byproviding a bypass path from the input cell to the output cell, a directanalog input cell function translation may be made to the output withoutgoing through the analog interconnect array 150. Further, by providing abypass path from the output of an input cell to the input of anotherinput cell, programmability of the analog input cell 300 may be enhancedby cascading different or similar functional blocks. For example, ifinput cell A is configured as a gain amplifier with a gain of 10, andinput cell B is configured also as a gain amplifier with a gain of 10,by cascading the two input cells, a gain amplifier with a gain of 100can be achieved. Other functions such as filters may also be configuredby cascading input cells

FIG. 4 is a schematic diagram of a programmable analog output cell 400according to an embodiment of the invention. In the illustratedembodiment, the output cell 400 includes a current-to-voltage converter402, a 2×2 interconnect matrix 404, a 2:2 multiplexer 410, a 10:1multiplexer 406, a 2:1 multiplexer 408, and an output comparator 414.The 2×2 interconnect matrix 404 directs the input signal (e.g., signalfrom the interconnect array 150 or directly from the input cell throughthe bypass path) to the analog output 416 and/or to the inputmultiplexer 410 of the output comparator 414. The 10:1 multiplexer 406directs one of the 10 reference values into the 2:1 multiplexer 408,which is used to pass a reference voltage or the output of theoperational amplifier 402 to the output comparator 414. The 2×2multiplexer 410 directs the selected reference voltage and the selectedinput signal to the output comparator 414. Furthermore, the comparator414 converts the analog signal into digital signal for interface with adigital array 162. The output comparator 414, in combination with the2:2 multiplexer 410, can compare any combination between the operationalamplifier output 420, the selected reference voltage 422, and the output424 of the adjacent input cell. It should also be noted that the outputcell 400 allows the input signal to be outputted as analog signalthrough an op-amp 412 to the analog output 416. This provides thearchitecture with the flexibility of being configured as providinganalog functions and/or analog functions interfacing with digitalfunctions. Sizes of the matrix and the multiplexers used in theexemplary embodiment are for illustrative purposes only. Hence, thesizes may be adjusted appropriately to configure the interface betweenthe analog portion 110 and the digital portion 160 of the mixed-modearchitecture 100.

There has been disclosed herein embodiments for re-configurable analogdevices and functions used in a mixed-mode integrated circuitarchitecture 100. The analog devices include re-configurable analoginput cells 112-118, programmable analog output cells 120-126, and aprogrammable interconnect array 150. The input cells 112-118 enableprogramming of a desired analog function using configuration switchesSW1-SW17. The interconnect array 150 converts the output signal of theanalog input cells 112-118 from voltage to current, and processes theconverted signal(s) by mixing/splitting. Once the signal(s) has beenprocessed, the interconnect array 150 converts the signal(s) fromcurrent to voltage, and directs the signal(s) to the output cell(s)120-126. The output cells 120-126 enable routing of the signals to acomparator 414 for conversion to digital signal.

While specific embodiments of the invention have been illustrated anddescribed, such descriptions have been for purposes of illustration onlyand not by way of limitation. The present invention should therefore notbe seen as limited to the particular embodiment described herein, butrather, it should be understood that the present invention has wideapplicability with respect to mixed-mode integrated circuit architecturegenerally. Throughout this detailed description, for the purposes ofexplanation, numerous specific details were set forth in order toprovide a thorough understanding of the present invention. It will beapparent, however, to one skilled in the art that the embodiments may bepracticed without some of these specific details. In other instances,well-known structures and functions were not described in elaboratedetail in order to avoid obscuring the subject matter of the presentinvention. For example, although the details for implementing theprogrammable digital array are not provided herein, it is understoodthat conventional programmable arrays, such as programmable logicdevices (PLD), field programmable gate arrays (FPGA), or evenmicroprocessors, may be used. Accordingly, all modifications,variations, or equivalent arrangements and implementations that arewithin the scope of the attached claims should therefore be consideredwithin the scope of the invention.

What is claimed is:
 1. A mixed-mode integrated circuit system,comprising: a plurality of analog input cells configured to programanalog functions; a plurality of analog output cells configured toprovide digital and/or analog outputs corresponding to said programmedanalog functions; an interconnect array to process said programmedanalog functions into signals indicative of said analog functions, saidinterconnect array selectively providing said signals to said pluralityof analog output cells; and a programmable digital portion.
 2. Thesystem of claim 1, further comprising: a voltage-to-current converter toconvert said programmed analog functions from voltage to current priorto being directed to the interconnect array for processing.
 3. Thesystem of claim 1, further comprising: a current-to-voltage converter toconvert said signals indicative of said analog functions from current tovoltage prior to being directed to said plurality of analog outputcells.
 4. The system of claim 1, wherein said interconnect array isconfigured to enable mixing of one or more of said programmed analogfunctions into one analog output cell.
 5. The system of claim 1, whereinsaid interconnect array is configured to enable splitting of oneprogrammed analog function into one or more analog output cells.
 6. Thesystem of claim 1, wherein said interconnect array is configured in amatrix format to select between mixing of one or more of said programmedanalog functions into one analog output cell and splitting of oneprogrammed analog function into one or more analog output cells.
 7. Thesystem of claim 1, further comprising: a plurality of direct analoginputs to allow input of analog signals into said interconnect array. 8.The system of claim 1, further comprising: a voltage reference generatorto provide voltage references to the analog input and output cells. 9.The system of claim 1, wherein one of said plurality of analog inputcells includes transistors, capacitors, adjustable resistors,configurations switches, and an operational amplifier to program adesired analog function.
 10. The system of claim 1, wherein said analoginput cell further includes a multiplexer to receive an input signalfrom an adjacent input cell, said multiplexer enabling cascading ofanalog functions to program complex functions.
 11. The system of claim1, wherein one of said plurality of analog output cells includes aninterconnect matrix to enable selection of inputs from adjacent inputcell to allow direct input of programmed analog function directly fromthe analog input cell, and from said interconnect array.
 12. The systemof claim 1, wherein one of said plurality of analog output dellsincludes a comparator to convert the programmed analog functions intodigital signal.
 13. The system of claim 1, wherein said programmabledigital portion includes a programmable logic device or FieldProgrammable Gate Array (FPGA)
 14. The system of claim 1, wherein saidprogrammable digital portion includes digital macrocells.
 15. A system,comprising: re-configurable input cells to select and program analogfunctions; and programmable output cells to receive said programmedanalog functions and to provide digital and/or analog output signalscorresponding to said programmed analog functions.
 16. The system ofclaim 15, further comprising: a programmable array to process saidanalog functions in a matrix format by combining signals from saidre-configurable input cells, and directing the processed signals to theprogrammable output cells.
 17. The system of claim 16, wherein theprogrammable array includes a plurality of voltage-to-current convertersto convert the output of the analog input function from voltage tocurrent prior to processing.
 18. The system of claim 17, furthercomprising: a plurality of current-to-voltage converters to convert saidprocessed signals from current to voltage prior to directing to theprogrammable output cells.
 19. A system, comprising: a plurality ofanalog input cells to provide a plurality of predefined analogfunctions; a plurality of analog output cells to generate digital and/oranalog output signals corresponding to said predefined analog functions;and a current sensing array to convert predefined analog functions fromsaid plurality of analog input cells into current signal, to mix anddirect said current signal, to convert said current signal into voltagesignal, and to selectively provide said voltage signal to said pluralityof analog output cells.
 20. The system of claim 19, wherein said currentsensing array is configured to select between mixing of one or more ofsaid predefined analog functions into one analog output cell andsplitting of one predefined analog function into one or more analogoutput cell.